Pulse width modulation (PWM), sometimes referred to as pulse duration modulation, is a signal processing technique which varies pulse width to obtain an improvement in overall efficiency performance. This is accomplished by representing a sample value of an input information signal by some property of a resultant pulse other than an amplitude value. Similarly, pulse amplitude modulation (PAM) is also a sampled data type of encoding where information is encoded into the amplitude of a train of finite width pulses. When PWM is used, the samples of a message are used to vary the duration of the individual pulses while PAM is an alternative means of obtaining a lower level output signal by reducing the pulse amplitude instead of duration. Thus with PWM, information is encoded into the time parameter instead of amplitude. The modulating wave may vary the time of occurrence of the leading edge, trailing edge or both edges of the resultant pulse train.
A PWM time signal can be converted into the frequency domain by fourier analysis. The frequency representation is comprised of desired DC energy as well as undesired AC terms. Preferably, the DC component is the desired representation of the information signal sample. As the time duration of the pulse width modulated signal decreases, relative to the maximum duration, an undesired AC signal potential increases relative to the desired DC signal component. During signal amplification, this results in a decrease in the DC to DC conversion efficiency and an increase in potential electromagnetic interference (EMI) which can be experienced within an associated communications product. Additionally, EMI may be exported to nearby electronic communications equipment which may effect other systems.
In a standard pulse width modulated amplifiers using a constant pulse amplitude and frequency, the output signal is preferably related to the pulse duration. For low level output signal, the undesired EMI increases as the pulse duration decreases from its maximum. Hence, an ideal PWM amplifier will have 100% efficiency but this efficiency will be reduced by the following factors:
1. Switching device resistance in series with the load impedance e.g. Rds (on) values; PA0 2. AC currents dissipated in the parasitic and desired real components in the load loop; PA0 3. Switching transit time resulting in node voltages across the switching devices during current flow; and PA0 4. The charging of large capacitances of each node associated with the switching devices.
A variety of techniques have been used in helping to offset these factors. These include minimizing the AC power dissipation at the amplifier output using an inductor placed in series with the load. This acts to increase the impedance to any AC signals at the sampling frequencies and their related harmonics. Additionally, increasing the sampling frequency works to reduce the AC dissipation, however, the associated transit and capacitance charging dissipation of the amplifier will also increase. At maximum power output, the minimum Rds(on) value maximizes efficiency. Since the capacitance charging is a fixed dissipation constant, this most often presents a set of tradeoffs which must be factored in to achieve optimized efficiency.